Compound semiconductors like gallium arsenide (GaAs) provide advantages over silicon for many applications, owing to their direct bandgaps and high electron mobilities. Examples range from efficient photovoltaic devices1, 2 to radio-frequency electronics3, 4 and most forms of optoelectronics5, 6. However, growing large, high quality wafers of these materials, and intimately integrating them on silicon or amorphous substrates (such as glass or plastic) is expensive, which restricts their use. Here we describe materials and fabrication concepts that address many of these challenges, through the use of films of GaAs or AlGaAs grown in thick, multilayer epitaxial assemblies, then separated from each other and distributed on foreign substrates by printing. This method yields large quantities of high quality semiconductor material capable of device integration in large area formats, in a manner that also allows the wafer to be reused for additional growths. We demonstrate some capabilities of this approach with three different applications: GaAs-based metal semiconductor field effect transistors and logic gates on plates of glass, near-infrared imaging devices on wafers of silicon, and photovoltaic modules on sheets of plastic. These results illustrate the implementation of compound semiconductors such as GaAs in applications whose cost structures, formats, area coverages or modes of use are incompatible with conventional growth or integration strategies.
Figures at a glance
Figure 1: Schematic illustration, optical and SEM images, and SIMS profile of GaAs/AlAs multilayers. 
a, Schematic illustration of a multilayer stack of GaAs/AlAs and schemes for release through selective etching of the layers of AlAs. b, Corresponding SIMS profile of this stack. c, Cross-sectional SEM image after partial etching of the AlAs layers. d, Optical image of a large collection of GaAs solar cells formed by release from a three-layer stack, and then solution casting onto another substrate. Inset, high magnification view. e, Cross-sectional SEM image of a 40 repeat multilayer stack of GaAs (200 nm)/AlAs with ultrathin (20 nm) AlAs sacrificial layers. Inset, high-magnification view. f, Cross-sectional SEM image (coloured) of a heterogeneous multilayer stack composed of three layers for MESFETs (green), one layer for an NIR detector (yellow) and one layer for a single junction solar cell (blue). The substrate is purple. Each of the device layers is separated by 20 nm AlAs (red). Details of stack design and corresponding SIMS profile are in Supplementary Information.
Figure 2: Multilayer GaAs MESFETs and logic circuits. 
a, Schematic illustration of a GaAs MESFET on a polyimide (PI) coated glass substrate. b, Optical image of arrays of MESFETs on glass substrate. Inset, a single MESFET with source (S), drain (D) and gate (G) metal layers. c, VDS (drain–source voltage) versus IDS (drain–source current) curves of MESFETs fabricated from first, second, third, fourth and fifth layers at gate–source voltages (VGS) of 0.4, 0.2, 0, -0.2, -0.4 and -0.6 V, from top to bottom. d, IDS versus VGS transfer curves of MESFETs fabricated from first, second, third, fourth and fifth layers, at VDS = 1.5 V. e, Amplitude plots for current gain (H21) and MAG measured from the fourth layer device. The unity current gain frequency (fT) and unity power gain frequency (fmax) are ~2 and ~6 GHz, respectively. f, Optical image of NAND and NOR gates on polyimide (VA, VB, input voltages for switching transistors; Vdd, drain voltage for load transistor; VO, output voltage). g, Output–input characteristics of NAND gates using devices from the first, second and third layers. h, As g but for NOR gates.
Figure 3: Multilayer GaAs NIR imagers. 
a, Schematic illustration of a GaAs metal–semiconductor–metal (MSM) NIR detector on a Si wafer coated with a photocurable polyurethane (PU). Inset, Schottky blocking diode (SD). b, Optical image of a NIR imager consisting of a 16 × 16 array of detectors (12 pixels are shown). Inset, a unit cell before interconnect metallization. c, I/V characteristics of a cell formed with material from the first, second, third and fourth layers. Open circles and lines correspond to responses in the dark and under NIR illumination (wavelength 830 nm), respectively. d, Photograph of an NIR imager mounted on a printed circuit board. e, Image acquired with an NIR imager formed with material from the second layer. f, As e but using material from the fourth layer. Insets in e and f correspond to objects that were imaged.
Figure 4: Multilayer GaAs single-junction solar cells. 
a, Schematic illustration of GaAs single-junction solar cell on a PET substrate coated with a photodefinable epoxy. b, Optical image of arrays of such devices formed on the source wafer. Inset, magnified view of top (n-type) and bottom (p-type) contacts. c, Representative light current density (J)-voltage (V) curves for Zn-doped solar cells formed from the first (top), second (middle) and third (bottom) layers, under AM1.5D illumination measured on the source wafer with a single-layer ARC of Si3N4. d, Short-circuit current density (Jsc), fill factor (FF) and open circuit voltage (Voc) of first, second and third layer devices. Error bars, s.d. e, IQE and EQE of first and second layer devices. f, Projected efficiencies (η) and Jsc values without ARC and with double-layer ARCs (DLARC; MgF2/ZnS) for devices formed using material from the first and second layers. g, Photograph of a solar module consisting of a 10 × 10 array of GaAs solar cells (each ~500 μm × 500 μm) on a PET substrate. h, Light current–voltage (I/V) and power–voltage (P/V) curves for such a module with parallel interconnection of 10 cells. i, As h but with series interconnection. Both measurements were made in a flat configuration.
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