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 18.06.2007   Карта сайта     Language По-русски По-английски
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Hybrid silicon evanescent devices

Alexander W. Fanga, E-mail The Corresponding Author, Hyundai Parka, Ying-hao Kuoa, Richard Jonesb, Oded Cohenc, Di Lianga, Omri Radayc, Matthew N. Sysaka, Mario J. Panicciab and John E. Bowersa
aDepartment of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA
bIntel Corporation, 2200 Mission College Blvd, SC12-326, Santa Clara, CA 95054, USA
cIntel Corporation, S.B.I. Park Har Hotzvim, Jerusalem, 91031, Israel

Available online 16 June 2007.

Si photonics as an integration platform has recently been a focus of optoelectronics research because of the promise of low-cost manufacturing based on the ubiquitous electronics fabrication infrastructure. The key challenge for Si photonic systems is the realization of compact, electrically driven optical gain elements. We review our recent developments in hybrid Si evanescent devices. We have demonstrated electrically pumped lasers, amplifiers, and photodetectors that can provide a low-cost, scalable solution for hybrid integration on a Si platform by using a novel hybrid waveguide architecture, consisting of III-V quantum wells bonded to Si waveguides.

The indirect bandgap of Si has been a key hurdle in the achievement of optical gain elements. Raman lasers and amplifiers[1], [2] and [3] have been demonstrated, and optical gain in nanopatterned Si4 has also been observed, but an electrically pumped all-Si gain element has yet to be realized. An alternative to creating an electrically pumped all-Si gain mechanism is to take prefabricated lasers and couple them to Si waveguides. However, because of the tight alignment tolerances of the optical modes and the need to align each laser individually, this method has a limited scalability and it is difficult to envision die attaching more than a few lasers to each chip without prohibitive costs.

We are developing wafer-scale approaches that could result in the simultaneous fabrication of thousands of lasers on a single Si wafer. Recently, we demonstrated an electrically driven laser5 and amplifier6 based on a hybrid waveguide structure that uses III-V quantum wells bonded to Si waveguides to achieve optical gain. In addition, under reverse bias operation, the same structure acts as a photodetector7. The lateral homogeneous nature of the III-V quantum layer structure allows the optical mode to be defined by the Si waveguide, leading to an alignment-free bonding process. Moreover, the mode lies primarily in the Si region, leading to low coupling losses from the active hybrid waveguide to passive Si waveguide regions. This architecture allows for thousands of lasers, amplifiers, and photodetectors to be fabricated in a single bonding step.

Device structure and optical mode characteristics

The cross section of the hybrid Si evanescent waveguide device is shown in Fig. 1. It consists of a III-V multiple quantum well epitaxial layer structure bonded to a Si-on-insulator (SOI) rib waveguide. The device fabrication process can be divided into three major parts. First, the Si waveguides and any other desired Si devices are fabricated in a complementary metal-oxide-semiconductor (CMOS) fabrication facility. Next, the III-V epitaxial layer structure is transferred to the Si waveguides through an O2 plasma-assisted, low-temperature bonding process. Finally, post-processing of the III-V layers is done after bonding to control the flow of current through the structure to ensure efficient optical gain to the waveguide mode. The details of the transferred epitaxial structure are shown in Table 1.

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Fig. 1. Cross section of the hybrid Si evanescent device. (Reprinted with permission from8. © 2007 Optical Society of America.)

Table 1.

The III-V epitaxial layer structure5.

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As stated above, the optical mode characteristics are determined by the Si rib waveguide dimensions. Fig. 2 shows the Beamprop calculated optical mode with a fixed waveguide height for various waveguide widths. It can be seen that as the Si waveguide becomes wider, the mode is pulled more into the Si region, with the same trend being seen for variation of the waveguide height. This feature can be used to tailor each device's optical gain characteristics. For example, lasers could be designed with narrower waveguides, which increase high modal gains to achieve lower thresholds, while amplifiers in an adjacent section of the wafer could be designed to have wide waveguide widths to increase the saturation power of the amplifier.

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Fig. 2. Calculated optical mode for waveguide widths of 2.5 μm and 3 μm.

Plasma-assisted low-temperature wafer bonding

A key step in the fabrication of this device platform is the bonding of the InP-based epitaxial layer structure to Si. Wafer bonding follows the Si waveguide processing on an SOI substrate and the growth of the III-V epitaxial layer structure on an InP substrate. The wafers undergo a rigorous surface cleaning that involves a solvent clean and a rinse with Tergitol, a mild detergent. The surface is inspected for particles under a Nomarski microscope at 20x magnification and the cleaning process is repeated until no particles are present. After cleaning, the surface oxides of the Si and InP are removed with buffered HF and NH4OH, respectively. After oxide removal, the samples are inspected, cleaned if necessary, and then undergo an ozone cleaning treatment. Next the surfaces are treated with an O2 plasma. The samples are then dipped in deionized (DI) water, dried with N2, and the top surfaces are placed in physical contact. At this point, a weak spontaneous bonding occurs. To strengthen the bond, the wafers are held together under vacuum at a pressure of 2 MPa and a temperature of 300°C for 12 hours. After bonding, the InP substrate is removed in a HCl solution.

Because of the thermal expansion coefficient mismatch of Si and InP (αSi = 2.6 × 10−6 K−1, αInP = 4.8 × 10−6 K−1), a low-temperature, O2 plasma-assisted bonding (<300°C) approach is preferred over the conventional direct wafer bonding to InP done at ≥600°C with other material systems such as GaAs9. The O2 plasma surface treatment prior to the contact of SOI and InP enhances the bonding strength in both physical and chemical ways. By careful control of the discharge conditions (radio frequency or RF power, chamber pressure, gas flow rate, etc.), O2 energetic ion bombardment can remove hydrocarbon and water-related species from the sample surface very efficiently. An ultrathin layer of oxide (<5 nm) grown by plasma oxidation10 turns the hydrophobic sample surfaces into very smooth (root mean square, rms <5 Å) and extremely hydrophilic surfaces, which are less sensitive to microroughness than hydrophobic surface11. The Si-O-Si bonds of the oxide (SOI side) are also found to be more strained than conventional oxides formed in the standard RCA-1 cleaning process or other hydrophilic wet-chemical treatments, indicating a greater readiness to break and form new bonds12. The post-O2 plasma surface treatment DI water dip further terminates the oxide surface with polar hydroxyl groups, OH, which form bridges between mating surfaces resulting in spontaneous bonding at room temperature. The final 300°C annealing process enhances out-diffusion of interface-trapped molecules and desorption of chemisorbed surface atoms, such as hydrogen, and activates the formation of covalent bonds to achieve higher bonding energies11. Fig. 3 shows a Nomarski photograph of the top surface of the epitaxial layer structure transferred to a SOI substrate at 600°C and 250°C. Crosshatching can be seen for the direct wafer bonding sample, which can lead to material quality degradation and scalability issues because of the accumulation of stress over larger samples sizes. In contrast, the low-temperature sample shows a very smooth surface morphology. In addition, since the bonded interface intersects the optical mode, it must be transparent at wavelengths longer than 1.1 μm and have a smooth morphology to minimize absorption and scattering losses. Full details of the hybrid device processing can be found elsewhere5.

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Fig. 3. Nomarski microscope images, showing the surface roughness of the transferred III-V surface at bonding temperatures of (a) 600°C and (b) 250°C.

Hybrid Si evanescent laser

The first electrically driven hybrid Si evanescent device demonstrated was the hybrid Si evanescent laser5. These devices had a waveguide height, width, and rib-etch depth of 0.76 μm, 2.5 μm, and 0.76 μm, respectively. The cavity for these lasers was made by dicing the ends of a hybrid waveguide and polishing them to a mirror finish, resulting in a cavity length of 850 μm.

The cross-sectional scanning electronic microscope (SEM) image of the fabricated device is shown in Fig. 4a. Fig. 4b shows seven Si evanescent lasers operating simultaneously. The chip shown has 36 lasers fabricated with a single bond step. The number of lasers shown operating at a single time is limited by the current experimental set up (the number of probes), and it is feasible to operate all the lasers simultaneously if the devices are wire bonded instead of relying on probing.

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Fig. 4. (a) Si evanescent laser device cross-sectional SEM image, (b) seven Si evanescent lasers operating simultaneously, (c) laser power out versus the drive current (LI curve), (d) laser spectrum for drive currents of 70 mA and 100 mA.(Reprinted with permission from5. © 2006 Optical Society of America.)

Fig. 4c shows the power out of the laser versus drive current (LI curve). The laser light is collected through one side of the laser through a lensed fiber while being driven at various currents. It can be seen that the laser operates at temperatures up to 40°C. Taking into account the measured 6 dB fiber coupling loss and the fact that light is only collected out of one of the two laser facets, the maximum output power and differential efficiency are estimated to be not, vert, similar14 mW and 12.7%, respectively.

Fig. 4d shows the laser spectrum for two drive currents. At 70 mA, the laser is right above lasing threshold. The standard Fabry-Perot fringes can be seen with a main lasing peak in the 1577 nm regime. At 100 mA, other wavelengths also begin to lase, as expected in a Fabry-Perot laser. A 15 cm−1 modal loss is measured in the long wavelength regime using the Hakki-Paoli technique.

Hybrid Si evanescent amplifier

We have reported6 hybrid Si evanescent amplifiers that consist of 1.36 mm long hybrid waveguides with a waveguide height, width, and rib-etch depth of 0.76 μm, 2 μm, and 0.76 μm, respectively. The facets were diced and polished at a 7° angle and coated with an antireflection single quarter-wavelength layer of Ta2O5 to minimize cavity effects caused by the facets. The quantum well confinement factor was calculated to be 3.4%.

The amplifiers were tested by launching a laser signal into one side of the device through a lensed fiber and collecting the amplified light with a subsequent lensed fiber on the opposite side of the device. Fig. 5a shows the transverse electric (TE) fiber-to-fiber gain as a function of current. Taking into consideration the measured 5 dB coupling loss for these waveguide dimensions, the chip gain is given on the secondary y-axis. The maximum chip gain for this length is not, vert, similar13 dB. It can be seen that at drive currents greater than 100 mA, the gain saturates, which can be attributed to thermal effects. The inset shows the net modal gain and material gain as a function of current density. Fig. 5b shows the TE fiber-to-fiber gain spectrum as a function of various drive currents. It can be seen that the peak gain occurs in the 1575 nm range with a full-width half-maximum of 62 nm at a 200 mA drive current.

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Fig. 5. (a) Si evanescent amplifier gain versus current. Inset: net modal gain extracted from the chip gain versus current density at 1575 nm. (b) Gain versus wavelength at different current levels. (c) Gain versus output power at 1575 nm. (d) 3 dB saturation output power versus confinement factor and different optical mode widths. (Reprinted with permission from6. © 2007 IEEE.)

The 3 dB output saturation power from the chip is measured to be 11 dBm, as shown in Fig. 5c. The 3 dB output saturation power can be written as:

Click to view the MathML source (1)

where G0 is the unsaturated chip gain, w is the optical mode width at the quantum well region, d is the total thickness of the active material, hν is the photon energy, dg/dN is the differential gain, and τ is the carrier lifetime. Fig. 5d shows the calculated 3 dB output saturation power with different confinement factors (Γ) and optical mode widths (w). The evanescent coupling scheme of the device structure typically provides 2% to 3% of the quantum well (QW) confinement factor, resulting in higher output saturation powers than amplifiers with centered quantum wells whose typical confinement factor is around 5% to 15%.

Device performance for digital data transmission is typically characterized with the use of eye diagrams. Eye diagrams consist of the superposition of transitions between one and zero bits forming an ‘eye’ such that the transient behavior between the bits can be analyzed. Eye closure as a result of carrier dynamics in semiconductor optical amplifiers (SOAs) is a major issue in the design of SOAs. Injecting a short, high-power optical pulse into a SOA will cause gain saturation instantaneously13. The slow gain-recovery process associated with carrier injection requires several hundred picoseconds to restore the unsaturated gain. In the case of pseudo-random bit sequences (PRBS), if the data rate is close to the gain-recovery time, the amplified output can be strongly degraded by pattern effects. Fig. 6a shows measured 10 Gbps non return to zero (NRZ) eye diagrams with three different input powers. The measured data agrees qualitatively with simulated eye diagrams, which are calculated using the rate equation model for multiple quantum wells14. A carrier lifetime of 1.1 ns results in the best agreement with the measured eye diagrams. The degradation of the Q factor of the signal can be observed with input power above −4 dBm.

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Fig. 6. Digital performance of a Si evanescent amplifier. (a) Simulated and measured eye diagrams. From left to right, input powers are −7 dBm, 2 dBm, and 5 dBm, respectively. The simulation agrees well with the measurement of a fitted carrier life time of 1.1ns, which is typical for quantum wells. (b) BER and eye diagrams. From left to right: 2.5 G back-to-back (B2B), 2.5 G amplified (Amp), 10 G B2B, 10 G Amp (low input, −16 dBm), 10 G Amp (high input, 2 dBm), 40 G RZ B2B, 40 G RZ Amp.

Bit error rate (BER) measurements are used to characterize digital performance when a device is used in a digital communications system. The BER measurements at three different data rates, 2.5 Gbps NRZ, 10 Gbps NRZ, and 40 Gbps return to zero (RZ), have been performed to investigate the power penalties imposed by the amplifier. For 10 Gbps and 40 Gbps, PRBS of 231-1 was used to carry out the BER test. A shorter sequence of 210-1 was chosen for 2.5 Gbps because of low-frequency cut off in the measurement system. The average input power is set to −16 dBm to keep the device unsaturated. A variable optical attenuator (VOA) is used between the output of the amplifier and the receiver (Rx) to adjust the received power. The power penalty of the amplifier is extracted by comparing the BER performances of the Tx-amplifier-Rx link with the back-to-back

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