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03.02.2011

Nanometer-Scale Oxide Thin Film Transistor with Potential for High-Density Image Sensor Applications



    Sanghun Jeon*, Sungho Park§, Ihun Song, Ji-Hyun Hur, Jaechul Park, Hojung Kim, Sunil Kim, Sangwook Kim, Huaxiang Yin, U−In Chung, Eunha Lee, and Changjung Kim




Semiconductor Device Laboratory and Analytical Engineering Center, Samsung Advanced Institute of Technology, Samsung Electronics Corporations, Yongin-Si, Gyeonggi-Do 446-712, Republic of Korea


ACS Appl. Mater. Interfaces, 2011, 3 (1), pp 1–6

DOI: 10.1021/am1009088

Publication Date (Web): December 20, 2010

Copyright © 2010 American Chemical Society

* Corresponding author. E-mail: sanghun1.jeon@samsung.com., †

Semiconductor Device Laborator, Samsung Advanced Institute of Technology.


, §

Current address: Department of Chemistry at Daejin University.


, ‡

Analytical Engineering Center, Samsung Advanced Institute of Technology.






Abstract



Abstract Image

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In−Ga−Zn−O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al2O3/SiO2) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.


http://server.ihim.uran.ru/files/info/2011/am1009088.pdf


 




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